The present invention relates to semiconductor devices and methods of making such devices. More particularly, the invention relates to solid state materials and to a novel method of aligning buried structures formed in such solid state materials.
The fabrication of integrated circuits (IC) devices on semiconductor wafers include various steps during which patterns are transferred from photolithographic masks on the wafers. The masking step involves an etching step and defines predefined areas to be exposed on the wafer for subsequent processing, for example, oxidation, metallization, or doping, among others. This photolithographic process is repetitively performed until desired patterns of materials are formed on the semiconductor wafer.
As the dimensions of these patterns become increasingly smaller, it is strictly required to accurately align the patterns previously formed on the semiconductor wafer with a pattern that is to be subsequently formed, and to minimize the misalignment between IC layers. To accurately carry out this process, the semiconductor industry employs alignment marks which are provided at predetermined position on the surface of a wafer, so that relative positioning between patterns is performed referring to these marks.
Typically, alignment marks are topographical patterns, such as squares, crosses or chevrons, among others, which are formed by etching into the wafer to provide slit patterns constituted of longitudinal indentations over specific intervals at semiconductor surface, an insulating layer or other layers of a semiconductor substrate.
The formation of alignment marks is typically executed simultaneously with, or after, other processes, for example the formation of metallization layers over a semiconductor substrate. In this case, the etching of the alignment mark must be conducted with extreme care, to avoid overetching of the substrate and/or of the underlying layers, which could be metal layers. Another problem posed by the formation of the alignment marks under these circumstances is the readability of the mark, particularly when an oxide layer covers the mark. As known in the industry, the formation of semiconductor devices requires, in most cases, a series of oxidation steps to form various oxide layers at different stages of processing. For example, new isolation processes such as shallow trench isolation (STI) necessitate a thick oxide layer formed over both the wafer and the alignment marks. When the thick oxide layer is later polished, typically by chemical mechanical polishing, to create a planar surface, the alignment marks on a new overlying layer on the wafer are flattened after planarization, causing alignment target reading problems.
Another problem encountered by conventional alignment processes relates to the alignment of various buried structures. As the semiconductor industry is exploring new ways of increasing the amount of active surface area on the integrated circuit chips, particularly on those employing monocrystalline semiconductor substrates, attempts to create and develop new technologies have been made continuously. For example, one technology proposed by the semiconductor industry is the so-called Silicon-On-Insulator (SOI) process, wherein oxygen atoms are implanted at high dose and energy to form a silicon dioxide insulating layer between the upper surface of the original monocrystalline substrate and the bottom bulk portion of the same substrate. Although the SOI devices have many advantages, such as reduced parasitic capacitance due to the buried insulating layer, the process is relatively expensive because of the high costs of implanting the oxygen atoms and curing of the implant-induced defects. Further, buried structures such as SOI devices are completely covered by the reformed monocrystalline semiconductor substrate and thus they become essentially non-readable for alignment purposes.
Accordingly, there is a need for an improved method of increasing the available active surface area on integrated circuit chips fabricated on monocrystalline substrates by forming buried structures within such substrates. There is also a need for a more advantageous alignment process for such buried structures formed in monocrystalline superconducting substrates. There is further a need for an improved metallization scheme which facilitates the formation of active devices on SOI substrates and on the more novel Silicon-On-Nothing (SON) substrates, as well as a need for accurate alignment of such metallization scheme with subsequently formed layers.
The present invention provides a method of forming an alignment mark for aligning a plurality of empty-spaced patterns formed in semiconductor monocrystalline substrates. According to an exemplary embodiment, alignment metal marks are formed of a conductive material having a melting temperature higher than the annealing temperature used to form the empty-spaced patterns. The alignment marks are formed prior to the formation of empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Holes could be next formed in the monocrystalline substrate to connect surfaces of the substrate with the previously formed empty-space patterns. The whole assembly is subsequently exposed to an oxidizing atmosphere so that the inner surfaces of the empty-space patterns are oxidized. The empty-space patterns could then be filled with a suitable conducting material to form, for example, buried conductors and/or buried plate patterns. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks. This way, a proper alignment of the semiconductor devices to the buried conductors and/or buried plate patterns is achieved.